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ASDL-7021 irda ? fir/vfir controller in tfbga package data sheet features general features ? interfaces with irda ? compliant ir transceiver up to vfir ? miniature 48 pin tfbga package height : 1.2 mm width : 4.0 mm depth : 4.0 mm ? 8-bit memory mapped interface ? input clock of 48 mhz ? 4 transmission speed in 3 blocks - sir block (2.4 to 115.2kbps) - fir block (1.152mbps for mir and 4mbps for fir) - vfir block (16mbps) ? operating temperature from -40 c ~ 85c - critical parameters are guaranteed over temperature and supply voltage ? core power supply = 1.8v clock power supply = 3.3v io power supply =1.8v, 2.5v, 3.3v ? ram block with on-chip bufer memory of 8kbyte x 2 bank confguration - 1 bank for external access x 8 bit width - 1 bank for internal access x 8 bit width through on-chip dma block - these 2 banks can be switched - each transmit and receive have their own bufer memory of 8kbyte x 2 description the ASDL-7021 is a new generation large scale integra - tion (lsi) irda controller supporting speeds of sir (up to 115kbps), mir(1.152mbps), fir(4mbps) and vfir (16mbps). it consists of irda control block, remote control block, timer control block, global control block including bufer memory and direct memory access control block (dma) integrated into one single chip. it has all the hardware including bufer memory and direct memory access (dma) that enables convenient access to its peripheral io and memories from system bus which is similar to simple memory devices. ASDL-7021 is a class of its own as unlike conventional lsi which utilizes external dma for implementing fast infrared transfer, complicated bus timing and required additional logic for its interface. ASDL-7021 utilizes two memory banks for external access and internal dma access; these 2 banks are interchange - able to prevent bus contention. these two banks can be switched using memory select function of the internal register and separates internal bus from external, which enables parallel operation of external microcontroller operation and internal irda data transfer operation. ASDL-7021 has embedded universal remote control (rc) function for general purpose remote control communica - tion. together with lite-on fir transceiver and irsimple software, ASDL-7021 is designed to provide industry a total solution for high speed wireless connectivity solution in miniature packaging. applications ? mobile data communication and universal remote control - mobile phones - pdas - digital still camera - printer - notebooks - handy terminal - dongles - industrial and medical instrument bank1 fir blo ck cp u dm a bank0 bank1 fir blo ck cp u dm a
figure 1a. pin layout of ASDL-7021 figure 1b. pin layout of ASDL-7021 (top view) features (cont.) ? infrared interface block - irda send/receive functions (irtx0, irrx0) - remote control send function (irtx1) ? dma block - dma transfer function between bufer memory and sir, fir, vfir block ? remote control block generate remote control burst signal ? timer block - 2 channels of generic 16 bit timer - 1 channel of mediabusy timer ? moisture level 3 ? lead-free and rohs compliant d1,d2,e2,e1,g1,g2,f1,f2 g3,f3,f4,g4,g5,f7,g6,g7 f6 e5 e6 d7 e7 d5 a6 b6 c7 b7 a7 a3 a2 b2 c1 a1 b3 c3 d3 e3 b1 d6 e4 f5 c2 c4 c5 c6 /xtalin /xtalout clkin clksel irda transceive r i/f irrxd0 irtx0 (irda) irtx1 (remote ) irout0 (irmode ) host i/f /cs a[7:0] gnd gnd gnd gnd gnd v io3 v io2 vio1 v io1 vddc vddk vddk vddk d[7:0] /we /oe /irq /sd /reset ir0ut1 (sd) ASDL-7021 internal clock external clock
application support information the application engineering group is available to assist you with the application design associated with ASDL-7021 fir/vfir controller. you can contact them through your local sales representatives for additional details. order information part number packaging type quantity asdl-70 tape and reel 4000 i/o pins confguration table pins description symbol pin(s) type bufer type (refer to figure 2) description power vddk c4,c5,c6 power .8v power vddc c power . v power vio e4,f5 power .8v, .5v, .v vio d6 power .8v, .5v, .v vio b power .8v, .5v, .v gnd a,b,c,d,e power gnd bus interface signals (vio1 voltage) a0-a7 d,d,e,e, g,g,f,f i i an 8-bit address signal line connects itself directly with an external address bus. it selects the internal bufer memory and the register addresses of each function module. with the assertion of the cs signal, a0 - a7 turn out to be valid, which decides the internal addresses. d0-d7 g,f,f4,g4 g5,f7,g6,g7 i/o io4 an 8-bit data signal line connects itself directly with an external data bus. it is a signal that performs data conversion with the internal bufer memory and each function module.the bus direction is determined by we and oe. /cs f6 i i cs is a chip select signal for the ic. asserting cs activates the external bus of this lsi. /we e5 i i the we signal turns the direction of a data bus to the input direction, and takes it into the ic for the internal bufer memory and registers designated by the address bus, at the start-up of the signal. /oe e6 i i the oe signal turns the data bus direction to the output direction, and outputs to the data bus the contents of the internal bufer memory and register designated by the address bus. /irq d7 o o4 this is a signal line that notifes to the outside that asdl-70 requests an interrupt.
4 other signals (vio1 voltage) /reset d5 i i this reset signal resets asdl-70 . /sd e7 i i (internal pulldown) . low: shutdown ic is suspending the clock supply to the core. the output signal retains the condition. . high: ic is keeping the clock supply to the core. however, when the externally connected quartz crystal is used with clksel=low, the oscillation of the quartz crystal is kept performed under the condition of clksel=low, and sd: low. when you want to stop the quartz crystal oscillation, you must set clksel=high. . after wake up from sd, the ic must be reset. clksel c i i this is used for selecting whether the input signal from clkin should be used for the clock input or whether the quartz crystal should be used at xtalin and xtalout. using quartz crystal, clksel = low, external quartz crystal is kept under oscillation clksel = high, external quartz crystal is suspending oscillation using clkin signal, set clksel = high infrared interface signal (vio2 voltage) irtxd0 b6 o o4 this outputs the irda infrared signal and remote control send signal. irtxd c7 o o4 this outputs the irda infrared signal and remote control send signal. irrxd0 a6 i i this inputs a signal from the infrared module. irout0 b7 o o4 this is an output signal for controlling the infrared module. irout a7 o o4 this is an output signal for controlling the infrared module. clock signal (vio3 voltage) clkin b i i clock input clock signal (vddc voltage) /xtalin a i you must connect quartz crystal to create a basic clock or input the clock from outside. usually you must connect the quartz crystal between xtalin and xtalout. the oscillation frequency of the crystal must be 48mhz. /xtalout a o test signal test b5 i i (internal pulldown) test signal (set to n.c). test a5 i i (internal pulldown) test signal (set to n.c). test a4 i i (internal pulldown) test signal (set to n.c). testse b4 i i (internal pulldown) test signal (set to n.c).
5 output bufertype figure 2. i/o description block diagram figure 3. block diagram of internal blocks of ASDL-7021 o4: iol=4ma,ioh=4ma(vio = 3.3v) iol=2.2ma,ioh=2.2ma(vio = 2.5v) iol=1.4ma,ioh=1.4ma(vio = 1.8v) i vio i(pulldown) o4 vio i(schmitt) vio vio io4 vio
6 block name base address ofset register name irda 0x0000 0000h irba0r(ir base address0 register) 000h irba r(ir base address register) 000h irba r(ir base address register) 000h irrsr(ir ring size register) 0004h irplc0r(ir physical layer confg0 register) (unused) 0005h irplc r(ir physical layer confg register) (unused) 0006h irplc r(ir physical layer confg register) 0007h irplc r(ir physical layer confg register) 0008h irc0r(ir confg0 register) 0009h irc r (ir confg register) 000ah irc r (ir confg register) 000bh irc r (ir confg register)(unused) 000ch ire0r(ir enable0 reg.) 000dh ire r (ir enablereg.) 000eh irmpl0r(ir max packet length0 reg.) 000fh irmpl r (ir max packet lengthreg.) 000h irrp0r(ir ring prompt0 reg.) 00h irrp r (ir ring prompt register reg.) (unused) 00h irrp r (ir ring prompt register reg.) (unused) 00h irrp r (ir ring prompt register reg.) (unused) 004h irrbc0r(ir receive byte count0 reg.) 005h irrbc r (ir receive byte count reg.) 006h irrrpr0r(ir rx ring pointer readback reg.) 007h irtrpr0r (ir tx ring pointer readback reg.) 008h irsf0r(ir sir flags0 reg.) 009h irsf r (ir sir flags reg.) 00 ah irlpc0r(ir latched phy confg0 reg.) 00 bh irlpc r (ir latched phy confg reg.) 00 ch irac0r(ir address compare0 reg.) 00 dh irac r (ir address compare reg.) 00 eh irac r (ir address compare reg.) 00 fh irac r (ir address compare reg.) 000h irlt0r(ir latency timer0 reg.) 00h irlt r (ir latency timer reg.) 00h irlt r (ir latency timer reg.) 00h irlt r (ir latency timer reg.) 004h irliv0r(ir led indicator and rx value0 reg.) 005h irliv r (ir led indicator and rx value reg.) (unused) 006h irliv r (ir led indicator and rx value reg.) (unused) 007h irliv r (ir led indicator and rx value reg.) (unused) 008h ircs0r(ir clock speed0 reg.) 009h ircs r (ir clock speed reg.) 00 ah ircs r (ir clock speed reg.) (unused) 00 bh ircs r (ir clock speed reg.) (unused) 00 ch irpm0r(ir power management reg.) 00 dh irpm r (ir power management reg.) (unused) 00 eh irpm r (ir power management reg.) (unused) 00 fh irpm r (ir power management reg.) (unused) 000h iris0r(interrupt status read back0 reg.) 00h iris r (interrupt status read back reg.) (unused) 00h iris r (interrupt status read back reg.) (unused) 00h iris r (interrupt status read back reg.) (unused) 004h irie0r (interrupt enable read back0 reg.) 005h irie r (interrupt enable read back reg.) (unused) 006h irie r (interrupt enable read back reg.) (unused) 007h irie r (interrupt enable read back reg.) (unused) registers descriptions
7 block name base address ofset register name irda 0x0080 (txfl fifo) 0000h txfl0r(tx frame length0 reg.) 000h txfl r(tx frame length reg.) 000h unused 000h txsr(tx status reg.) 0004h txfa0r(tx frame address0 reg.) 0005h txfa r(tx frame address reg.) 0006h txfa r(tx frame address reg.) 0007h txfa r(tx frame address reg.) 0008h txsir(tx status incrementreg.) 0009h txfcr(tx frame count reg) irda 0x0090 (rxfl fifo) 0000h rxfl0r(rx frame length0 reg.) 000h rxfl r(rx frame length reg.) 000h unused 000h rxsr(rx status reg.) 0004h rxfa0r(rx frame address0 reg.) 0005h rxfa r(rx frame address reg.) 0006h rxfa r(rx frame address reg.) 0007h rxfa r(rx frame address reg.) 0008h rxsir(rx status incrementreg.) global control 0x00a0 0000h mtdr (memory transmit data reg) write only 0000h mrdr(memory receive data reg) read only 000h mcr(memory control reg.) 000h gisr(global interrupt status reg.) 000h irsr (ir select reg.) 0004h ior(ir output reg) 0005h iir(ir input reg) 0006h isier(ir sir interupt enable reg) 0007h isisr(ir sir interupt status reg) dma control 0x00b0 0000h dmacr(dma control reg) remote control 0x00c0 0000h rccclr(remote control carrier count low reg) 000h rccchr(remote control carrier count high reg) 000h rcllr(remote control length low reg.) 000h rclhr(remote control length high reg.) 0004h rccr(remote control control reg) 0005h rccrclr(remote control carrier rx count low reg) 0006h rccrchr (remote control carrier rx count high reg) timer control 0x00d0 0000h tssr0(timer source setting reg.0) 000h tier0(timer interrupt enable reg.0) 000h tcsr0(timer contorol status reg.0) 000h tcmlr0(timer compare mach low reg.0) 0004h tcmhr0(timer compare mach high reg.0) 0005h tclr0(timer count low reg.0) 0006h tchr0(timer count high reg.0) 0x00e0 0000h tssr (timer source setting reg.) 000h tier (timer interrupt enable reg.) 000h tcsr (timer contorol status reg.) 000h tcmlr (timer compare mach low reg.) 0004h tcmhr (timer compare mach high reg.) 0005h tclr (timer count low reg.) 0006h tchr (timer count high reg.) 0x00f0 0000h tssr (timer source setting reg.) 000h tier (timer interrupt enable reg.) 000h tcsr (timer contorol status reg.) 000h tcmlr (timer compare mach low reg.) 0004h tcmhr (timer compare mach high reg.) 0005h tclr (timer count low reg.) 0006h tchr (timer count high reg.)
8 absolute maximum ratings for implementations where case to ambient thermal resistance is 50c/w. parameter symbol min. max. units core power supply voltage vddk -0. vio+0. v clock power supply voltage vddc -0. .6 v io power supply voltage vio -0. .6 v input output voltage vi/vo -0. .6 v operating environnent temperature ta -40 85 c storage temperature ts -40 50 c electrical specifcations (dc) specifcations (min. & max. values) hold over the recommended operating conditions unless otherwise noted. unspecifed test conditions may be anywhere in their operating range and vio = 3.3+0.33v vio= 3.3+/-0.33v, ta=-40 to +85c parameter symbol min. typ. max. units conditions core power supply vddk .6 .8 .98 v clock power supply vddc .97 . .6 v io power supply vio .97 . .6 v input low voltage vil 0.8 v lvttl input high voltage vih .0 v lvttl switch threshold vt .5 v lvttl schmitt-trigger Cve threshold voltage vt- 0.8 . v lvttl schmitt- trigger +ve threshold voltage vt+ .6 .0 v lvttl input leakage current iin -0 0 a vi=vio or gnd tri-state output leakage current ioz -0 0 a vi=vio or gnd output low voltage vol 0.4 v iol = ~6ma output high voltage voh .4 v ioh = ~6ma input pull-down resistance rpd 40 75 90 k? vin =vio current (vfir running state) C vddk ioz k 8.6 0.5 .5 ma sd:high current (idle state) C vddk iozk 8.0 0. .0 ma sd:high current (vfir running state) C vio iozio 940 a sd:high current (idle state) C vio iozio 4 0 a sd:high current (vfir running state) C vio iozio 5 a sd:high current (idle state) C vio iozio 0. a sd:high current (idle state) C vio iozio 8 a sd:high clock power supply current-vddc iozc 4.0 4.8 5.9 ma capacitor 0pf
9 vio= 2.5+/-0.25v, ta=-40 to +85c parameter symbol min. typ. max. units conditions core power supply vddk .6 .8 .98 v clock power supply vddc .97 . .6 v io power supply vio .5 .5 .75 v input low voltage vil 0.5*vio v cmos input high voltage vih 0.65*vio v cmos switch threshold vt .5 v cmos schmitt-trigger Cve threshold voltage vt- 0.5*vio 0.94 v cmos schmitt- trigger +ve threshold voltage vt+ .4 0.65*vio v cmos input leakage current iin -0 0 a vi=vio or gnd tri-state output leakage current ioz -0 0 a vi=vio or gnd output low voltage vol 0.4 v iol = . ~8.8ma output high voltage voh .85 v ioh = . ~8.8ma input pull-down resistance rpd 45 5 90 k? vin =vio vio= 1.8+/-0.18v, ta=-40 to +85c parameter symbol min. typ. max. units conditions core power supply vddk .6 .8 .98 v clock power supply vddc .97 . .6 v io power supply vio .6 .8 .98 v input low voltage vil 0.*vio v cmos input high voltage vih 0.7*vio v cmos switch threshold vt 0.85 v cmos schmitt-trigger Cve threshold voltage vt- 0.*vio 0.65 v cmos schmitt- trigger +ve threshold voltage vt+ .08 0.7*vio v cmos input leakage current iin -0 0 a vi=vio or gnd tri-state output leakage current ioz -0 0 a vi=vio or gnd output low voltage vol 0.4 v iol = 0.7 ~5.6ma output high voltage voh 0.75*vio v ioh = 0.7 ~5.6ma input pull-down resistance rpd 80 0 50 k? vin =vio
0 shutdown currents (internal clock is used) [1] parameter min. typ. max. unit conditions note shutdown current (vddk) 7.8 8.8 9.7 m a /sd: low clksel: low clkin: low external quartz crystal is kept under oscillation shutdown current (vddk) 0.4 m a /sd: low clksel: high clkin: low external quartz crystal is suspending oscillation clock power supply current (vddc) 0. m a /sd: low clksel: high clkin: low shutdown current (vio ) 0. m a /sd: low clksel: high clkin: low shutdown current (vio ) 0. m a /sd: low clksel: high clkin: low shutdown current (vio ) 0. m a /sd: low clksel: high clkin: low shutdown currents (external clock is used) [1] parameter min. typ. max. unit conditions note shutdown current (vddk) . .9 m a /sd: low clksel: high clkin: 48mhz /xtalin: low clock power supply current (vddc) 0. m a /sd: low clksel: high lkin: 48mhz /xtalin: low shutdown current (vio ) 0. m a /sd: low clksel: high clkin: 48mhz /xtalin: low shutdown current (vio ) 0. m a /sd: low clksel: high clkin: 48mhz /xtalin: low shutdown current (vio ) 8.5 m a /sd: low clksel: high clkin: 48mhz /xtalin: low (1) test conditions: - /reset = high (vio1) - a[7:0] = must be driven either high (vio1) or low (0v) - d[7:0] = must be driven either high (vio1) or low (0v) - /cs = high (vio1) - /we = high (vio1) - /oe = high (vio1) - irrxd0 = high (vio2)
clock standards standard values of the system clock input frequency: 48mhz 100ppm input duty: must be within 50% 5%. power-up procedures v t vddk(=1.8v) vddc,vio(=1.8 to 3.3v) v t vddk(=1.8v) vddc,vio(=1.8 to 3.3v) v v recommended power-up procedure allowable limit of power-up procedure turn on the core power supply vddk before you turn on the vddc and vio power supply and shut it down later if you want to turn on the core power supply vddk after you turn on vddc and vio power supply, you must keep v = vio-vddk < 0.5v during the time before vddk becomes stabl e
2) stabilization time of power-on oscillation (internal clock is used) a.c timing 1) reset input timing item symbol min typ max unit reset pulse width trst 50 ns /reset - on oscillation t rst oscillation stabilization term internal clock vc c /reset soc1 t rst /sd t parameter symbol typical value power-on oscillation stabilization time t soc 0ms reset pulse width t rst 50ns
3) return oscillation stabilization time via clksel item symbol min typ max unit clksel return oscillation stabilization time tsoc 0 msec oscillation stabilization time when the quartz crystal is connected oscillation stabilization term internal clock clksel /reset t soc1 t rst stabilization time of power-on oscillation (external clock is used) parameter symbol typical value power-on oscillation stabilization time t soc 50ns reset pulse width t rst 50ns oscillation stabilization term external clock vc c /reset soc1 t rst /sd t
4 4) read operations item symbol min max unit address setting time tasr 0 ns address retaining time tahr 0 ns data delay time tdrd 80 ns read pulse amplitude trdw 80 ns output retaining time tdhw 0 ns turnaround time toet 50 ns /c s a[7:0] /o e d[7:0] /o e valid data t drd t dhw t wth t rdw t asr t ahr valid data t oet
5 5) write operations item symbol min max unit address setting time tasw 0 ns address retaining time tahw 0 ns write pulse amplitude twrw 50 ns data setting time tdsw 0 ns data retaining time tdhw 0 ns turnaround time twet 70 ns /c s a[7:0] /w r d[7:0] /w e valid data t dsw t dhw t asw t ahw valid data t wrw t wet
6 6) send pulse amplitude item symbol conditions min typ max unit sir send pulse amplitude 9,600bps ttspw /6 pulse amplitude 0.7 0.8 0.9 s 9,00bps 0. 0.4 0.5 s 8,400bps 5.6 5.8 5.9 s 57,600bps .4 .40 .47 s 5,00bps .70 .7 .74 s .6s pulse amplitude .6s fxed typ register irplc r,irplcr pw[4:0] = 0x4e 0.8nsec step changeable .665 .7 .769 s sir send cycle 9,600bps ttsrt 04.0 04. 04. s 9,00bps 5.0 5. 5. s 8,400bps 5. 6.0 6. s 57,600bps 7. 7. 7.4 s 5,00bps 8.5 8.6 8.7 s mir send pulse amplitude .5mbps ttmpw typ register irplc r,irplcr pw[4:0] = 0x4e 0.8nsec step changeable 6 7 8 s mir send cycle .5mbps ttmrt 854 868 875 s fir send pulse amplitude 4mbps ttfpw 4 5 6 s fir send cycle 4mbps ttfrt 500 s vfir send pulse amplitude 6mbps ttfpw 4.0 4.7 4.0 s
7 ASDL-7021 package dimension:
8
9 ASDL-7021 tape and reel dimension:
0 pin 1 orient at ion orient at io n cover ta pe carrier t ap e
figure 4. baking conditions chart baking conditions package temp time in bulk 5 c f 4hours baking should only be done once. recommended storage conditions storage temperature 0 c to 0 c relative humidity below 60% rh time from unsealing to soldering after removal from the bag, the parts should be soldered within 7 days if stored at the recommended storage con - ditions. if times longer than 7 days are needed, the parts must be stored in a dry box. moisture proof packaging all ASDL-7021 options are shipped in moisture proof package. once opened, moisture absorption begins. this part is compliant to jedec level 3. no yes yes yes no no units in a sealed moisture-proof package package is opened (unsealed) parts are not recommended to be used environment less than 30c and less than 60%rh package is opened less than 168 hours package is opened less than 15 days perform recommended baking conditions no baking is necessary
recommended refow profle process zone symbol d t maximum d t/ d time or duration heat up p, r 5c to 50c c/s solder paste dry p, r 50c to 00c 60s to 80s solder refow p, r p, r4 00c to 55c 55c to 00c c/s -6c/s cool down p4, r5 00c to 5c -6c/s time maintained above 7c > 7c 60s to 50s peak temperature 60c time within 5c of actual peak temperature > 55c 0s to 40s time 5c to peak temperature 5c to 60c 8mins the refow profle is a straight-line representation of a nominal temperature profle for a convective refow solder process. the temperature profle is divided into four process zones, each with diferent d t/ d time tem - perature change rates or duration. the d t/ d time rates or duration are detailed in the above table. the tempera - tures are measured at the component to printed circuit board connections. in process zone p1 , the pc board and ASDL-7021 pins are heated to a temperature of 150c to activate the fux in the solder paste. the temperature ramp up rate, r1, is limited to 3c per second to allow for even heating of both the pc board and ASDL-7021 pins. process zone p2 should be of sufcient time duration (100 to 180 seconds) to dry the solder paste. the temper - ature is raised to a level just below the liquidus point of the solder, usually 200c (392f). process zone p3 is the solder refow zone. in zone p3, the temperature is quickly raised above the liquidus point of solder to 255c (491f) for optimum results. the dwell time above the liquidus point of solder should be between 20 and 40 seconds. it usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder con - nections. beyond a dwell time of 40 seconds, the inter - metallic growth within the solder connections becomes excessive, resulting in the formation of weak and un - reliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200c (392f), to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25c (77f) should not exceed 6c per second maximum. this limitation is necessary to allow the pc board and ASDL-7021 pins to change dimensions evenly, putting minimal stresses on the ASDL-7021. 50 100 150 200 250 300 t-tim e (seconds) 25 80 120 150 180 200 230 255 0 t - temperature (c ) r1 r2 r3 r4 r5 217 max 260c 60 sec to 180 sec above 217 c p1 heat u p p2 solder paste dry p3 solder reflow p4 cool down
figure a1. block diagram of ASDL-7021 interface with recommended transceiver and host microcontroller appendix a: general application guide for the ASDL-7021 integrated fir/vfir irda controller ASDL-7021 fir/vfir irda controller host microcontroller address bus data bus /cs /o e /we /irq /sd /reset clksel clkin irtx0(irda) irtx1(remote irrxd0 irout0(irmode/s clk) irout1 (sd) irda transceiver (can be stc or non-stc with/without rc) recommended fir hw: asdl-3023, hsdl-3021, hsdl-3020 and hsdl-3220 for company and product information, please go to our web site: www.liteon.com or http://optodatabook.liteon.com/databook/databook.aspx data subject to change. copyright ? 007 lite-on technology corporation. all rights reserved.

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